1. Field of Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a polysilicon gate electrode.
2. Description of Related Art
In the deep submicron regime of semiconductor manufacturing, feature size, contact area, and junction depth are all reduced. To improve the performance of the integrated circuit device and to lower resistance and resistance/capacitance delay, a metal silicide layer is frequently formed as part of a gate electrode in addition to a polysilicon layer. Because the metal silicide layer can be formed without performing a photolithographic operation, the method of forming a silicide layer is often referred to as a self-aligned silicide (Salicide) process. Most salicide layers are formed using titanium silicide (TiSi.sub.x). Titanium silicide is often used because it has a low resistivity. In addition, a titanium silicide layer can be formed in a controlled manner so that quality and reliability can always be maintained.
However, with the reduction of dimensions of a polysilicon gate electrode, forming a high-quality metal silicide layer above the polysilicon gate electrode is becoming difficult. Growth of the metal silicide layer is stunted by the high level of stress between the metal silicide layer and the polysilicon layer and/or the small number of nucleation sites. Therefore, quality of the silicide layer is likely to deteriorate, sheet resistance of the silicide layer is likely to increase, and performance of the gate electrode will be compromised. For a device whose line width is smaller than 0.18 .mu.m, quality of the silicide layer is often improved by performing a pre-amorphization implant (PAI) before carrying out the salicide process. The PAI converts a surface layer of the polysilicon into an amorphous silicon layer so that sheet resistance of the subsequently formed salicide layer decreases.
FIGS. 1A through 1C are schematic, cross-sectional view showing the progression of steps for forming a conventional gate electrode. As shown in FIG. 1A, a semiconductor substrate 100 having device isolation structures 102 therein is provided. A gate oxide layer 104 and a doped polysilicon layer 106 are sequentially formed over the substrate 100. The gate oxide layer 104 and the doped polysilicon layer 106 are patterned to form a gate electrode 108. To prevent diffusion of light due to surface roughness, an anti-reflection coating 110, typically made from silicon oxynitride, is formed over the polysilicon layer 106 before the gate oxide layer 104 and the polysilicon layer 106 are patterned. After the polysilicon layer 106 is patterned, hot phosphoric acid is used to remove the anti-reflection coating 110. However, in the process of removing the anti-reflection coating 110, a portion of the doped polysilicon layer 106 may be damaged by phosphoric acid. Therefore, a portion of the polysilicon layer in the gate structure may peel off resulting in a degradation of device's performance characteristics.
As shown in FIG. 1B, an pre-amorphization implant (PAI) is carried out implanting arsenic ions into the polysilicon gate electrode 108 so that a surface layer of the polysilicon layer 106 is broken down into an amorphous silicon layer 112. The amorphization of the polysilicon layer 106 facilitates the subsequent formation of a silicide layer. Source/drain regions 114 having a lightly doped drain (LDD) structure is formed in the substrate 100 on each side of the gate electrode 108.
However, the arsenic (atomic weight=74.9) ions used in the PAI has a relatively high atomic weight. Due to the presence of many large grains inside the polysilicon layer 106, arsenic ions is able to move along grain boundaries and contact surfaces of the polysilicon layer 106 and the gate oxide layer 104. Ultimately, the arsenic ions will end up in the channel region of the substrate 100 leading to an intensification of kink effect and the downgrading of device quality.
A layer of titanium (not shown in the figure) is sputtered over the substrate 100. Using a rapid thermal process, metal in the titanium layer reacts with silicon in the doped polysilicon layer 106 and silicon in the source/drain regions 114 to form a titanium silicide layer 116. The unreacted titanium is removed by wet etching to form the structure as shown in FIG. 1C.
In the self-aligned silicide process, some of the dopants within the polysilicon layer 106 will hinder the diffusion of silicon to the titanium layer. The prevention of silicon by dopants is referred to as a dopant effect. Without enough silicon to react with titanium to form a titanium silicide layer, the formation of a high-quality silicide layer is almost impossible.